Semiconductor devices are found in many products in the fields of entertainment, communications, networks, computers, and household markets. Semiconductor devices are also found in military, aviation, automotive, industrial controllers, and office equipment. The semiconductor devices perform a variety of electrical functions necessary for each of these applications.
The manufacture of semiconductor devices involves formation of a wafer having a plurality of die. Each semiconductor die contains hundreds or thousands of transistors and other active and passive devices performing a variety of electrical functions. For a given wafer, each die from the wafer typically performs the same electrical function. Front-end manufacturing generally refers to formation of the semiconductor devices on the wafer. The finished wafer has an active side containing the transistors and other active and passive components. Active and passive devices can also be formed on the backside of the wafer. Back-end manufacturing refers to cutting or singulating the finished wafer into the individual die and then packaging the die for structural support and environmental isolation.
Semiconductor devices come in a variety of package types and perform specific functions. Some common types of semiconductor devices are integrated circuits (ICs) and discrete devices, such as transistors, diodes, rectifiers, transit voltage suppressors, silicon controlled rectifiers (SCR), and thyristors. Discrete semiconductor devices perform specific functions such as signal rectification and power transfer. For example, a thyristor is a solid state discrete semiconductor device with four layers of alternating n-type and p-type semiconductor material, i.e., p-n-p-n or n-p-n-p. The thyristor operates as a switch, conducting when the gate receives a current pulse, and continuing to conduct while forward biased. An IC contains hundreds or thousands of transistors and other semiconductor components necessary to perform more complex analog and digital functions.
Many discrete semiconductor devices, such as diodes, SCRs, and thyristors, are manufactured by a planar process or mesa process. FIG. 1 illustrates a cross-sectional view of a conventional diode 10 containing a p-n junction, e.g., rectifier, small signal, or Zener. Diode 10 is made with a planar process. A n+ substrate 12 is shown with n− epitaxial (epi) layer 14 formed on substrate 12. Substrate 12 provides structural support to the device. A p+ region 16 is formed in epi layer 14. The planar process will have a surface silicon dioxide (SiO2) layer formed over the device. The p-n junction is formed between n− epi layer 14 and p+ region 16. Substrate 12, epi layer 14, and region 16 can be formed with opposite conductivity types, i.e., p+ substrate, p− epi layer, and n+ well.
FIG. 2 shows a conventional transistor 20 made with a planar process. An n+ substrate 22 is shown with n− epi layer 24 formed on substrate 22. Substrate 22 provides structural support to the device. A p well 26 is formed in epi layer 24. An n+ region 28 is formed in p well 26. The planar process will have a surface SiO2 layer formed over the device. The n-p-n transistor is formed between n− epi layer 24, p well 26, and n+ region 28. Substrate 22, epi layer 24, well 26, and region 28 can be formed with opposite conductivity types, i.e., p+ substrate, p− epi layer, n well, and p+ region.
FIG. 3 shows a conventional diode 40 containing a p-n junction made with a mesa process. An n+ substrate 42 is shown with n− epi layer 44 formed on substrate 42. Substrate 42 provides structural support to the device. A p+ layer 46 is formed over epi layer 44. Contours 48 are formed in epi layer 44 and layer 46 to build the mesa between the contours. The p-n junction is formed between n− epi layer 44 and p+ layer 46. Substrate 42, epi layer 44, and layer 46 can be formed with opposite conductivity types, i.e., p+ substrate, p− epi layer, and n+ layer.
Planar and mesa processes impose certain limitations on the manufacturing process and design criteria that can affect the electrical parameters of the device. An important consideration is the behavior of the p-n junction under high voltage. A high voltage creates electric field fringing because the junction terminates at the device surface. Accordingly, silicon p-n junctions normally breakdown at the surface of the device. The fringing electric field reduces the device breakdown voltage. To compensate, guard rings or field plates are often used to spread out the fringing electric field.
Depending on the specific manufacturing steps, the planar process can have surface state limitations that degrade the reverse breakdown voltage and increase the p-n junction leakage current. The surface state limitations further restrict the level of breakdown voltage that can be obtained even if other design parameters are proper. The planar process typically requires deep junctions to decrease the radius of curvature of the diffused junction. However, the deep junction has the undesired effect of increasing the sidewall capacitance of the p-n junction and adds to the manufacturing cost.
In a mesa manufacturing process, photolithography and etching are used to define the p-n junction. Again, an important consideration is the behavior of the p-n junction under high voltage. Contouring the shape of the mesa can improve the breakdown voltage as shown in FIG. 3, but adds complexity and cost to the manufacturing process. The removal of silicon to form the contours and mesa makes wafer handling problematic and leads to wafer breakage and yield loss.
The planar and mesa processes have used different types of passivation films to help maintain a stable reverse breakdown voltage. For example, a high temperature oxidation can be used to passivate the p-n junction, followed by additional thin passivation layers to obtain a stable junction. In adapting various passivation films, surface states and charges within the film must be closely monitored to prevent undesirable characteristics. The additional passivation layers require more handling that further leads to wafer breakage and contamination that can degrade the electrical parameters. The passivation films also add cost, complexity, and variation to the manufacturing process which can degrade the film characteristics, as well as the p-n junction. The potential for wafer breakage limits the use of large diameter wafers which increases manufacturing costs.
Another deficiency is the relatively poor electrical stability when the semiconductor device is subjected to high temperature reverse bias (HTRB) at elevated temperature, such as 150° C. to 175° C. While surface passivation films may provide satisfactory results at lower operating conditions, long term high temperature stability is preferred as a measure of stability for the semiconductor device, especially for military and space applications.
In the manufacture of ICs, an isolation diffusion process is commonly used to make analog and digital circuits. The isolation diffusion process uses photolithography and etching to define the isolation surface area. The resolution of the photolithographic process defines the width of the isolation pattern. The isolation diffusion process imposes certain design limitations that affect the electrical parameters and die size, including the width of the isolation pattern, thickness of the epi, and resistivity that must be scaled to the desired voltage. In general, the higher the voltage, the higher the resistivity and the thicker the epi layer. The isolation diffusion process can cause lateral junction-spreading from all edges of the defining mask pattern at the surface of the die which imposes a volume space problem at the junction. The spreading extends laterally as the diffusion is driven downward to the substrate, which requires a substantial amount of silicon to isolate each active device area.
Depending on the specific manufacturing steps, the isolation diffusion process can have surface state limitations that degrade the reverse breakdown voltage and increase the p-n junction leakage current. The surface state limitations further restrict the level of breakdown voltage that can be obtained even if other design parameters are proper. Accordingly, the high voltage process typically requires deep junctions to decrease the radius of curvature of the diffused junction. However, the deep junction has the undesired effect of increasing the sidewall capacitance of the p-n junction and adds to the manufacturing cost.